El uso de la música rap en la enseñanza del español como lengua extranjera

Universidad de Sevilla. Grado en Filología Hispánic

Supporting task creation inside FPGA devices

The most common model to use co-processors/accelerators is the master-slave model where the slaves (coprocessors/ accelerators) are driven by a general purpose cpu. This simplifies the management of the accelerators because they cannot actively interact with the runtime and they are just passive slaves that operate over the memory under demand. However, the master-slave model limits system possibilities and introduces synchronization overheads that could be avoided. To overcome those limitations and increase the possibilities of accelerators, we propose extending task based programming models (like OpenMP [1] or OmpSs) to support some runtime APIs inside the FPGA co-processor. As a proof-of-concept, we implemented our proposal over the OmpSs@FPGA environment [2] adding the needed infrastructure in the FPGA bitstream and modifying the existing tools to support creation of children tasks inside a task offloaded to an FPGA accelerator. In addition, we added support to synchronize the children tasks created by a FPGA task regardless they are executed in a SMP host thread or they also target another FPGA accelerator in the same co-processor

Hypogravity research and educational parabolic flight activities conducted in Barcelona: a new Hub of innovation in Europe

We report on different research and educational activities related to parabolic flights conducted in Barcelona since 2008. We use a CAP10B single-engine aerobatic aircraft flying out of Sabadell Airport and operating in visual flight conditions providing up to 8 seconds of hypogravity for each parabola. Aside from biomedical experiments being conducted, different student teams have flown in parabolic flights in the framework of the international contest ‘Barcelona Zero-G Challenge’, and have published their results in relevant symposiums and scientific journals. The platform can certainly be a good testbed for a proof-of-concept before accessing other microgravity platforms, and has proved to be excellent for motivational student campaigns.Peer ReviewedPostprint (author's final draft

Automatic generation and testing of application specific hardware accelerators on a new reconfigurable OpenSPARC platform

Specific hardware customization for scientific applications has shown a big potential to address the current holy grail in computer architecture: reducing power consumption while increasing performance. In particular, the automatic generation of domain-specific accelerators for General- Purpose Processors (GPPs) is an active field of research to the point that different leading hardware design companies (e.g. Intel, ARM) are announcing commercial platforms that integrate GPPs and FPGAs. In this paper we present a new framework with a holistic approach that addresses the challenge of design exploration of specific application accelerators. Our work focuses on a target platform consisting of a GPP with a reconfigurable functional unit. The framework includes a reconfigurable 1-core 1-thread OpenSPARC with a new programmable specific purpose unit (SPU) inside the OpenSPARC core. In order to program the SPU we have developed an automatic toolchain that profiles an application and discovers its main computing bottlenecks. With that information our toolchain is able to both design hardware specific accelerators that can be automatically mapped in the aforementioned SPU, and generate the binary code necessary to run the application using those accelerators. The OpenSPARC with the new specific application accelerators, defined in a Hardware Description Language, can then be executed and measured. Still awaiting further development, nowadays our framework is a proof-of-concept that shows that this kind of systems can be developed and programmed as easily as a GPP. In a near future it would be the source of very interesting information about the capabilities and drawbacks of those mixed GPP-FPGA systems.Postprint (published version

Task scheduling sensitivity to L1 cache settings on an area-constrained 32-core RISC-V processor

High-performance applications are highly sensitive to memory performance characteristics. While programs with comparatively low memory-to-computation ratio are less likely to be hampered by limited memory bandwidth, most parallel applications will be severely impacted by the absence of hardware support for low-latency inter-thread synchronization and data sharing. In this paper, we report a design exploration that sought to identify the cache configuration that maximizes performance of task parallel OpenMP workloads running on a Linux-capable 32-core RISC-V system. We show that, under the constraints of a U200 Alveo FPGA, the best single-level cache configuration consists in 160 KB of coherent, core-private data caches, with a 32/128 split among instruction and program data. With such configuration, we have achieved speedups of up to 28x and 19x for the nbody and cholesky applications, respectively

Estudio de la reactividad vascular en aortas de ratones deficientes en APO-E

64 p.La aterosclerosis es una afección crónica, causa de diversas enfermedades cardiovasculares. Su etiología multifactorial desencadena un proceso pro-inflamatorio que termina en el daño de los vasos sanguíneos. La disfunción endotelial, caracterizada por un desbalance en la producción de factores relajantes y contráctiles derivados del endotelio, se reconoce como un paso previo al desarrollo de aterosclerosis.Se investigó la reactividad vascular en ratones deficientes en ApoE (ApoE+/- como modelo de dislipidemia y disfunción endotelial) alimentados con dieta normal y se los comparó con ratones Wild type (C57B1/6). Para esto se extrajo la arteria aorta de los ratones y se trabajó con la técnica de los anillos aórticos, la cual fue optimizada antes de comenzar la investigación. La reactividad vascular se midió a través la relajación de los anillos aórticos con acetilcolina (0,01, 0,1; 1, 5 y 10 μM) previa contracción con fenilefrina 5μM. La viabilidad de las preparaciones fue corroborada antes de la contracción con fenilefrina, mediante la aplicación al sistema de 60 mM de KCl.La técnica fue exitosamente optimizada y permitió llevar a cabo el estudio. Los resultados mostraron que los anillos aórticos de los ratones deficientes en ApoE contrajeron más que los WT frente a KCl (p = 0,0383), siendo la tensión de precarga óptima a 1,5 g para ambos grupos. La contracción con fenilefrina no mostró diferencias significativas entre ambos grupos, mientras que la relajación inducida por acetilcolina fue menor en ratones ApoE+/- que en ratones Wild type (p= 0,005). Estos datos sugieren una posible disfunción endotelial en los ratones ApoE+/-

Aprendizaje cooperativo en cursos multidisciplinares

La enseñanza de contenidos técnicos en grupos multidisciplinares es una tarea compleja debido a la diversidad de los conocimientos iniciales de los alumnos implicados. Sin embargo esta dificultad puede llegar a convertirse en una poderosa herramienta. En este artículo se presenta la experiencia obtenida durante una asignatura de software libre impartida a un grupo multidisciplinar formado por alumnos de distintas carreras técnicas. La base de nuestra propuesta es obligar a los estudiantes a cooperar forzando grupos compuestos por alumnos de diferentes carreras. Este tipo de agrupación obliga a los alumnos a realizar trabajo cooperativo y aprendizaje entre iguales, lo que les permite desarrollar habilidades tanto técnicas como profesionales. Nuestros resultados muestran que con este enfoque se consiguen buenos resultados tanto en el aprendizaje como en la aceptación por parte de los alumnos de la asignatura y del método de enseñanza.Peer Reviewe

Does international patent collaboration have an effect on entrepreneurship?

.Entrepreneurship is one of the main pillars of growth in any economy. Achieving a high rate of entrepreneurship in a region has become the priority objective of governments and firms. However, in many cases, new firm creation is conditioned by relations or collaboration in innovation with agents from other countries. Previous literature has analyzed the mechanisms that foster entrepreneurship. This paper attempts to shed light on the influence of international patent collaboration (IPC) on entrepreneurial activity at country level taking into account the timing of this relationship. An empirical study is proposed to verify whether IPC leads to greater entrepreneurship and to analyze the gestation period between international patenting actions and firm creation. Using the Generalized Method of Moments, the two hypotheses proposed were tested in a data panel of 30 countries for the period 2005–2017. Results show the influence of IPC in promoting entrepreneurship in the same year, but especially in the following year. The study offers implications for entrepreneurs and public agents. IPC affects the integration and interaction of international agents in a country, favors the production of new knowledge, and increases positive externalities in a territory. All this facilitates the creation of new companies with a high innovative component.S

jPET 2.0: un generador automático de casos de prueba sobre programas Java

JPet lleva desarrollándose varios años a fin de convertirlo en una herramienta competitiva en el campo del software testing. Se encarga de obtener casos de prueba (test-cases) de código java que garanticen el recubrimiento óptimo del mismo. En su comienzo la forma en que jPet mostraba la información a los usuarios no era fácil de entender, lo que hacía que no fuera útil durante el desarrollo de software. En la actualidad, se ha solucionado este problema guardando la información necesaria de los casos de prueba en ficheros .xml, mostrando al desarrollador de una manera más gráfica y sencilla el trabajo realizado. La herramienta incorpora un visor en el que se puede comprobar el valor de los datos antes y después de la ejecución del código, así como la posibilidad de ver la traza de un caso de prueba en concreto. En este proyecto vamos a ampliar jPet añadiéndole la funcionalidad de generar tests en código java a partir de los casos de prueba almacenados en los ficheros .xml. De esta manera, el desarrollador puede verificar el funcionamiento del código que pretende testear. Los tests contienen todo lo necesario para su ejecución en java, pero están escritos a modo de plantilla por lo que, aunque ayudan al desarrollador ahorrándole tiempo, es necesaria sucolaboración para que recobren sentido y pasen a ser tests válidos. [ABSTRACT] Jpet has become a competitive tool for software testing over the years. It obtains java code test-cases that ensures an optimal coverage. From its beginnings, showing data and explaining it wasn’t an easy task, so Jpet was not useful for software developing. Nowadays, this problem has been solved by saving test-cases relevant data to .xml files, guiding software developers through a more graphic and comprehensive way of the work carried out by Jpet. It has a budget that may be interesting for developers, a graphic interface in which you can check data values before and after running the piece of software tested and see a concrete test-case tracing painted in a glowing green. So now we are going to expand and continue this ongoing project by adding functionality to generate java code unit tests (junits) using the test-cases above-mentioned. Those tests can run on Java but they are just templates. Although it will certainly help developers saving their time, they need to be accordingly modified to apply

Performance analysis of a hardware accelerator of dependence management for taskbased dataflow programming models

Along with the popularity of multicore and manycore, task-based dataflow programming models obtain great attention for being able to extract high parallelism from applications without exposing the complexity to programmers. One of these pioneers is the OpenMP Superscalar (OmpSs). By implementing dynamic task dependence analysis, dataflow scheduling and out-of-order execution in runtime, OmpSs achieves high performance using coarse and medium granularity tasks. In theory, for the same application, the more parallel tasks can be exposed, the higher possible speedup can be achieved. Yet this factor is limited by task granularity, up to a point where the runtime overhead outweighs the performance increase and slows down the application. To overcome this handicap, Picos was proposed to support task-based dataflow programming models like OmpSs as a fast hardware accelerator for fine-grained task and dependence management, and a simulator was developed to perform design space exploration. This paper presents the very first functional hardware prototype inspired by Picos. An embedded system based on a Zynq 7000 All-Programmable SoC is developed to study its capabilities and possible bottlenecks. Initial scalability and hardware consumption studies of different Picos designs are performed to find the one with the highest performance and lowest hardware cost. A further thorough performance study is employed on both the prototype with the most balanced configuration and the OmpSs software-only alternative. Results show that our OmpSs runtime hardware support significantly outperforms the software-only implementation currently available in the runtime system for finegrained tasks.This work is supported by the Spanish Government through Programa Severo Ochoa (SEV-2015-0493), by the Spanish Ministry of Science and Technology through TIN2015-65316-P project, by the Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272) and by the European Research Council RoMoL Grant Agreement number 321253. We also thank the Xilinx University Program for its hardware and software donations.Peer ReviewedPostprint (published version